The present invention relates generally to delay elements and more specifically to voltage-controlled delay elements in an integrated circuit.
Many circuits require that a particular delay be introduced into a circuit path, and there exist many techniques for accomplishing this. One way is to insert an appropriate number of logic gates or inverters into the path, which is appropriate when the necessary delay is known at the time the circuit is being designed. Since this is not always the case, controllable delay elements have been developed. One such controllable delay element uses a current-starved inverter to control the timing of signal edges (transitions) at the output terminal of the delay element relative to the timing of the edges at the input terminal.
FIG. 1A is a schematic of a representative delay circuit 10 using what is known as a current-starved inverter. The illustrated circuit includes a voltage-controlled current-limiting transistor in order to delay the rising edge of an input pulse. It is also known to have a pair of voltage-controlled current-limiting transistors to delay both edges of the pulse.
The circuit includes a p-channel transistor 12 and an n-channel transistor 15 in a standard CMOS inverter configuration, with an input terminal 17 and an output terminal 18, but is modified to include a current limiting n-channel transistor 22 between transistor 15 and ground. Transistor 22 has its gate coupled to a control voltage that determines the maximum circuit that can flow through the transistor. Output terminal 18 is coupled to the input terminal 25 of an inverter 27, the output terminal 28 of which defines the output terminal of the delay element. Output terminal 18 is characterized by some capacitance, shown by a capacitor 30, drawn in phantom. This capacitance may be an actual circuit element or may be the input capacitance of the following stage (inverter 25). Output terminal 18 will be referred to as the storage node.
The operation of the circuit in response to a rising edge at input terminal 17 can be better understood if reference is made to the timing diagram of FIG. 1B. Consider an initial condition where input terminal 17 (the common gate connection for transistors 12 and 15) has been low for a relatively long time. This turns transistor 12 on and transistor 15 off, and thus allows the storage node to charge up to the supply voltage through transistor 12. Thus the storage node is high and output terminal 28 is low.
The rising edge at input terminal is shown as occurring at a time T.sub.in, whereupon transistor 12 turns off and transistor 15 turns on, thus allowing the storage node to commence discharging. While transistor 22 remains in saturation its high drain impedance limits the rate at which this discharge can occur, however, and so the voltage on the storage node commences to fall approximately linearly at a rate that depends on the control voltage. At a later time T.sub.out, the voltage will have fallen to a level V.sub.X that is low enough to cause inverter 27 to begin outputting a high.
However, since the storage node is discharging at a controlled rate, the output transition from inverter 27 is not sharp. Thus the rising edge at output terminal 28 is delayed by a controlled amount, but is not as well-defined as the input rising edge. Moreover, since the node may not have fully discharged by the time a later pulse occurs, the effective delay may not be stable. Rather, the resultant delay may depend on the past history of charging and discharging of the storage node.
Developing the control voltage CTL for such a delay element can introduce difficulties in very high speed computer systems. Such systems are generally characterized by a shared high-speed clock that is used for timing and control throughout the circuits of the computer. Such systems are also characterized by noise and voltage transients on the power supply. Such systems can be very sensitive to even slight timing deviations in control signals which may run through a delay element. As a result, any circuit used to develop a control voltage in such a system must be synchronized with the timing signals of the circuit and must be insensitive to transient voltage fluctuations in the power supply. Otherwise, the delay element can introduce errors in the timing control of the circuit.